I. Field of the Invention The invention generally relates to integrated circuits and in particular to constant transconductance CMOS bias circuits for biasing NMOS differential pairs such as those employed in differential amplifiers.
II. Description of the Related Art NMOS differential pairs ac commonly employed within integrated circuits as high-speed components of differential amplifiers, sample and hold circuits, and the like. Constant transconductance bias circuits are employed in connection with the NMOS differential pairs for reducing or eliminating temperature and process variations of the gm of the differential pair. By way of example, the operation of a constant transconductance bias circuit is described in the following in connection with a differential pair containing an NMOS differential pair.
FIG. 1 illustrates a simple NMOS differential pair 10. The pair of NMOS devices 12 and 14 have rates connected to a pair of voltage input lines 16 and 18, respectively. A transconductance (g.sub.m) of the differential pair is .DELTA.i/.DELTA.V.sub.in where .DELTA.V.sub.in is the input voltage differential and .DELTA.i is the current through one of the devices of the differential pair. To prevent temperature and process variations from affecting the gm of the differential pair, the pair is biased by a bias voltage applied to the gate of an NMOS device 24 connected between the sources of devices 16 and 18 and ground. The bias voltage is generated by a bias circuit 26 which operates to generate a constant transconductance (g.sub.m) bias signal despite temperature and process variations. Briefly, the bias circuitry includes a pair of NMOS devices 28 and 30 connected between a pair of nodes A and B and ground, respectively. A pair of PMOS devices 32 and 34 arc connected, respectively, between nodes A and B and the positive voltage source. Gates of NMOS devices 28 and 30 are connected to node A. Gates of NMOS devices 32 and 34 are connected to B. A transconductance-setting resistor 36 is connected between the source of device 30 and ground. Resistor 36 is typically located off-chip to permit the resistance to be set after chip fabrication for better tolerance.
In use, bias circuitry 26 operates to generate a bias current that sets the transconductances of NMOS devices 12 and 14 of the differential pair to an amount inversely proportional to the resistance of transconductance-setting resistor 36. The bias circuit is, in effect, a modification of a MOS self-biasing Widlar current source, well known in the art. The constant transconductance of the NMOS devices of the differential pair may be established using the following equations (with the various terms in the equations having their standard definitions in the art): EQU vgs1=vgs2+IR EQU vgs2=vgs1+I.multidot.R
Since
##EQU1## B=.mu.nCoxW/L
and ##EQU2##
then
Solving for ##EQU3##
yields ##EQU4##
Thus, disregarding body effects the transconductances of the devices of the differential pair are merely inversely proportional to the resistance of the transconductance-setting resistor. Unfortunately, in practical integrated circuits, body effects can pose a significant problem. Briefly, body effects relate to a modification of the threshold voltage Vt caused by a voltage difference between source and substrate. The change in voltage threshold is proportional to the square root of the voltage between the source and the substrate. Differences in voltage between the source and the substrate occurs as a result of voltage drop across transconductance-setting resistor.
In the circuit of FIG. 1, the change in threshold voltage results in two separate problems. The first problem occurs from the variations in source voltage between NMOS devices 28 and 30 of the bias circuitry. Since the source of NMOS device 30 is at a different voltage from that of device 28, the transconductance is not merely proportional to the resistance of resistor 36 but is instead given by the following equation: ##EQU5##
where
This formula for transconductance may be derived from the following set of equations: EQU vgs1=vgs2+IR-vterr
##EQU6##
and since ##EQU7##
Then ##EQU8##
Solving for ##EQU9##
yields EQU g.sub.m =2+L .multidot.B.multidot.I
and finally ##EQU10##
The second body effect problem occurs as a result of absolute differences between the sources of devices 28 and 30 of the bias circuitry and devices 12 and 14 of the differential pair. The absolute current generated in the bias cell is proportional to the threshold voltage, and therefore any variances between the source voltages will result in a different transconductance value. Since the input common mode voltage to the differential pair is fixed, the source voltage of devices 12 and 14 will vary with process causing a non-tracking transconductance. As a result, temperature and process variations are not fully compensated for by the CMOS bias circuitry of FIG. 1 resulting in uncertainties in the accuracy of the output of the differential pair.
As can be appreciated, it would be highly desirable to provide an improved constant transconductance bias circuit for use with an NMOS differential pair that substantially eliminates variations caused by body effects and it is to that end that aspects of the invention are primarily directed.